1. Field of the Invention
This invention relates generally to interfacing modules in host or device adapters, and in particular to bus structures and methods for interconnecting modules within a multiple I/O bus interface integrated circuit.
2. Description of Related Art
Prior single chip host adapters have included a plurality of modules and an on-chip processor that controls operation of the modules. For example, U.S. Pat. No. 5,659,690, entitled "Programmably Configurable Host Adapter Integrated Circuit Including a RISC Processor, " issued on Aug. 19, 1997 to Stuber et al., which is incorporated herein by reference, had an internal bus that coupled the various modules to a sequencer that included a RISC processor.
Specifically, a SCSI module 130 (FIG. 1), a sequencer 120, data FIFO memory circuit 160, a memory 140, and a host interface module 110 were interconnected by an internal chip I/O bus CIOBUS, which was used for control of host adapter integrated circuit 100 both by a host microprocessor 170 through a host adapter driver 165 and by sequencer 120. The internal chip I/O bus CIOBUS included (i) a source bus with separate eight bit address and data buses, (ii) a destination bus with separate eight bit address and data buses, and (iii) a plurality of control signal lines, i.e., a chip source read enable line CSREN-, a chip destination write enable line CDWREN-, and a bus busy line CRBUSY. Internal chip I/O bus CIOBUS supported high speed normal operations that were controlled by sequencer 320 as well as slower but extended operations during error recovery that were controlled by the host adapter driver using the host microprocessor.
The splitting of the internal chip I/O bus CIOBUS into source and destination buses allowed each sequencer instruction to be completed in a single sequencer clock cycle, as opposed to the multiple cycles needed on a shared bus. Further, in some cases, a write operation and a read operation were performed simultaneously over internal chip I/O bus CIOBUS.
One problem encountered in implementing such a host adapter with an internal chip I/O bus CIOBUS is including hardware logic on the chip which controls the number of bus clock cycles for a particular module to complete a transaction over the internal bus. The predicted performance of a particular module is not known until late in the design process because the performance of the module is dependent upon resources on the chip that the module must use. Consequently, the hardware logic necessary to control the number of bus clock cycles cannot be designed until the design of all the modules is complete. This inhibits parallel design efforts of the complete chip and introduces delays in the time to market.
In addition, some circuits may perform somewhat differently from that predicted during design. Consequently, the hardware circuit that controls the number of bus clock cycles may not be adequate. This typically requires either fabrication of a new chip, or alternatively a software design around which permits operation of the module, but results in reduced performance. Typically, the software design around included a sequence of no operation instructions in the firmware for the on-chip sequencer. A method and structure are needed that eliminates the need for a separate centralized hardware circuit for each module to control the number of bus clock cycles required for a transaction over the bus.